Application of alignment marks to wafer

ABSTRACT

The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure consisting a non-metal is produced in an extensive metal layer and the semiconductor disk is subsequently planed in said region with the help of chemical and mechanical polishing. The structural sizes in the metal layer and the chemical-mechanical polishing process are adjusted to each other, in such a way that the small part non-metal structure protrudes above the extensive metal layer after polishing.

FIELD OF INVENTION

The invention relates to a method of applying alignment marks to asemiconductor wafer.

BACKGROUND

U.S. Pat. No. 5,786,260 discloses a method of applying alignment marksto a semiconductor wafer in which depressions are formed in a surfaceregion of the semiconductor wafer, lands being formed between thedepressions, an intermediate layer then being applied and then aninsulating layer or else a metal layer. During a subsequent CMP process,the insulating layer or the metal layer is removed, by using the dishingbehavior, in such a way that the edges of the alignment marks areexposed and stand out. A subsequent etching step for the remainingremoval of the insulating layer or metal layer in the depressions isspecified as optional.

U.S. Pat. No. 6,051,496 discloses the use of a stop layer during the CMPprocess, said layer being deposited on a dielectric layer having landsand depressions, specifically in particular in the case of a CUdamascene.

U.S. Pat. No. 6,080,636 discloses a production process for aphotolithographic alignment mark by means of a CMP process.

U.S. Pat. No. 6,020,263 discloses a method of exposing alignment marksfollowing a CMP process on tungsten metal.

The structuring of semiconductor wafers in order to producemicroelectric components is carried out almost entirely nowadays withthe aid of lithographic techniques. In this case, the structures areinitially produced via a photo mask in a thin radiation-sensitive resistlayer, normally an organic photoresist layer, which is applied to thesemiconductor wafer. By means of a suitable developer, the irradiated orunirradiated regions are then removed. The resist pattern produced inthis way is used as a mask for a subsequent process step, for exampleetching or ion implantation, with which the pattern is transferred intothe semiconductor structure layer lying underneath. The resist mask isthen dissolved away again.

In this case, for the quality of the lithographic method it is criticalto transfer the resist structure in correct position to thesemiconductor layer lying underneath. In this case, it is in particularnecessary to align the exposure device accurately in relation to thesemiconductor wafer in order to form the mask structure. In order toalign the exposure device, therefore, alignment marks are generallyapplied to the semiconductor wafer. These alignment marks are generallya structure comprising bars and lines which, in general, are executed inthe kerf region of the semiconductor wafer. The kerf region of thesemiconductor wafer represents a region about 50 to 100 μm wide betweenthe individual chips on the semiconductor wafer which, when thesemiconductor wafer is subsequently broken up into the individual chips,is then destroyed. However, the alignment operation is difficult when anadditional, optically non transparent layer is applied, which is neededfor example for the production of a capacitor, and therefore thealignment mark structure lying underneath in the semiconductor wafercannot be registered optically. In such a case, the application of thealignment marks to the semiconductor wafer in the prior art is thencarried out in such a way that, during the etching of the precedingstructure into the semiconductor wafer, at the same time the bars andlines are etched into the kerf area, the alignment masks being designedin such a way that during the following process steps, including thedeposition of the optically non transparent layer, said alignment marksare no longer completely filled. The topology of the alignment marks onthe semiconductor wafer can then be registered by means of opticalalignment mark detection methods and can be used to align the exposuredevice.

However, this manner of forming the alignment marks proves to beunsuitable in particular when it is intended to be carried out in thecontext of the damascene technique, which is used substantially forstructuring a metallization plane. In the damascene technique, which isprimarily used for structuring copper, in order to produce the metalwiring, at the location of the conductor tracks depressions are etchedinto the oxide lying underneath. In this etching step, the alignmentmark structure is then also formed in accordance with the conventionalmethod. There then follows the sputtering on or deposition of a thinstart layer to form a nucleus for the subsequent metal deposition overthe entire area. By means of chemical-mechanical polishing of the metallayer down as far as the surface of the etched trenches, the desiredconductor tracks are then produced. Since, in the damascene method,substantially perfect planarization of the metal layer is carried out,the topology of the alignment marks is also largely leveled during thechemical-mechanical polishing, so that said alignment marks no longerstand out following the application of a following, optically nontransparent layer. Furthermore, in particular in the copper damascenemethod, the trenches etched for the alignment marks also cannot beformed in such a way that these are not filled up completely during thecopper deposition, since copper always begins to fill all the trenchesfrom the bottom up, irrespective of their width, during the depositionmethods which are normally used, and it is therefore not possible eitherto produce any voids, that is to say cavities, in the trenches, whichthen lead to a topology of the alignment marks on an optically nontransparent layer that is subsequently deposited.

SUMMARY

In order to solve this problem, therefore, also in the prior art, inparticular in the damascene method, a topology of the alignment marks isproduced by means of a further lithographic and etching step, whichitself requires only inaccurate alignment. For this purpose, followingthe production of the alignment marks, and the subsequent deposition ofthe optically non transparent layer, the alignment mark structure istransferred via a dedicated photo mask to a thin radiation-sensitivelayer which is applied to the optically non transparent layer. Thealignment marks are then exposed by a subsequent etching step. However,this additional lithographic and etching step is complicated andexpensive.

It is therefore an object of the present invention to provide a simpleand cost-effective method of applying alignment marks to a semiconductorwafer which may be used in particular in conjunction with structuring ofthe semiconductor wafer with the aid of the damascene technique.

According to the invention, to apply alignment marks, an intricatestructure consisting of a non metal is produced in a large-area metallayer on at least one area of a semiconductor wafer. This area of thesemiconductor wafer having the large-area metal layer is then planarizedby means of chemical-mechanical polishing, the non metal structure inthe metal layer and the chemical-mechanical polishing process beingcoordinated with each other in such a way that the non metal structurestands out from the large-area metal layer.

Forming the alignment marks in accordance with the invention follows themodel of the damascene technique, but as opposed to the conventionalalignment mark design, a structure consisting of a non metal is producedin a large-area metal layer. This design makes it possible to makespecific use of two effects generally viewed as negative duringplanarization with the aid of the chemical-mechanical polishing.

This is because, during chemical-mechanical polishing, large-area metalsurfaces, if they are to be leveled, tend to be removed to too great anextent, that is to say tend to a dishing behavior. Then, in thestructure according to the invention, this leads to the intricate nonmetal structure present in the metal layer standing out, so that atopology that can be used as alignment marks is produced on a nontransparent layer which is subsequently applied.

Furthermore, in order to make the alignment marks contrasty, use canalso be made of the effect that occurs during chemical-mechanicalpolishing, that intricate non metal structures in a large-area metallayer, if the latter is to be planarized, likewise tend to be removed totoo great an extent as compared with the surrounding metal layer, thatis to say tend to erode, and therefore to form trenches in the metallayer. This trench formation of the alignment marks then ensures atopology on the non transparent layer which is subsequently applied,which is suitable for aligning an exposure device.

Depending on the design of the chemical-mechanical polishing operationand the design of the metal surface and the non metal structurecontained therein, it is therefore possible to cause the non metalstructure to stand out owing to a dishing behavior of the metal surfaceor this non metal structure to form trenches in the metal surface owingto an erosion behavior, which is then reflected in a topology on the nontransparent layer arranged above it.

According to a preferred embodiment, the application of the alignmentmask is carried out in the damascene technique, the large-area metallayer being deposited onto a layer consisting of a dielectric and havinglarge-area depressions. In this case, between the dielectric layer andthe metal layer, the further thin intermediate layer is provided inorder to form a nucleus for the metal deposition and as a diffusionbarrier.

The chemical-mechanical polishing process is carried out in two stages,the metal layer being removed in a first stage and being stopped on theintermediate layer lying underneath. During this first polishing step,dishing takes place in the large metal surfaces between the projectingdielectric structures, the intermediate layer on the projectingdielectric structures also partly being removed. In a second polishingstep, the intermediate layer on these projecting dielectric structuresis then removed, the polishing operation being stopped in thedielectric. During this second polishing operation, intensiveoverpolishing of the intermediate layer, and therefore erosion of thedielectric layer lying underneath, take place, so that trenches formbetween the large-area metal layers and then still remain detectable asalignment marks following the application of a non transparent layer.

This method sequence makes it possible, in particular when copper isused as the metal layer and tantalum/tantalum nitride as theintermediate layer, to use the formation of alignment marks also withinthe context of copper metallization in order to form conductor tracks.

The invention will be explained in more detail using the appendeddrawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a possible embodiment of the method according to theinvention of applying alignment marks in the context of coppermetallization with the aid of the damascene method,

FIG. 1A showing the layer structure before chemical-mechanicalpolishing,

FIG. 1B after a first polishing step and

FIG. 1C after a second polishing step; and

FIG. 2 shows an apparatus for chemical-mechanical polishing,

FIG. 2A showing a plan view and

FIG. 2B showing a sectional view.

DETAILED DESCRIPTION

Integrated circuits are generally produced on the semiconductor waferswith the aid of lithographic methods. In this case, each structurallevel is first produced via a photo mask in a thin radiation-sensitivelayer deposited onto the semiconductor wafer, generally an organicresist layer, and then transferred into the semiconductor layer lyingunderneath in a special etching method. In this case, care must be takenthat the structures lying one above another and belonging to theintegrated circuits are arranged in an accurate position in relation toone another, in order to achieve the highest possible integrationdensity. In this case, for an accurately positioned arrangement it iscritical that the exposure device for superimposing the mask structureis aligned exactly with a structure already present on the semiconductorwafer.

In order to align the exposure device, alignment marks are applied tothe semiconductor wafer, preferably in a kerf area 1 which is 50 to 100μm wide and which is subsequently used to break up the semiconductorwafers into the individual chips. Here, the alignment marks have to bedesigned in such a way that they produce a topology in the layer appliedto the alignment marks which may then be registered optically.

In the following text, the production according to the invention of suchalignment marks will be presented within the context of copperstructuring, which is carried out in the damascene technique.

In order to produce the copper wiring in the damascene technique, at thelocation of the conductor tracks depressions are etched asanisotropically as possible into a dielectric layer 2 which is appliedto the semiconductor wafer and preferably consists of silicon oxide. Atthe same time as this etching of the depressions for the conductortracks, further large-area depressions 3 are etched into the dielectriclayer 2, preferably in the kerf area 1 of the semiconductor wafer,narrow lands 4 remaining in the dielectric layer between theseadditional large-area depressions 3, as shown in FIG. 1A.

In the area of the conductor tracks, in the damascene method, anintermediate layer is then applied, preferably either by means ofsputtering on or CVD deposition. This intermediate layer ensures,firstly, reliable separation of the copper from the dielectric and fromthe semiconductor substrate lying underneath. In this case, the materialpreferably used for the intermediate layer is an tantalum/tantalumnitride double layer. As shown in FIG. 1A, this intermediate layer 5 isalso applied in the area of the additional depressions 3 in thedielectric layer 2, which are implemented in the kerf area 1 of thesemiconductor wafer. Then, copper in a thickness of about 1 μm isdeposited over the entire semiconductor wafer, that is to say both inthe conductor track area and in the kerf area 1, electrolytically orchemically in a current-free manner. This then results in an overallstructure in the kerf area 1 as shown in FIG. 1A.

In order to work out the alignment marks, a two-stagechemical-mechanical polishing process is then used. FIG. 2 shows,schematically, an apparatus for chemical-mechanical polishing, a planview being illustrated in FIG. 2A and a section along the A line in FIG.2B. On a rotatably arranged polishing table 10 there is arranged aresilient, perforated pad 11 which contains a polishing agent 12. Thepolishing agent 12 is supplied to the pad 11 via a polishing-agent feed13. For the purpose of chemical-mechanical polishing, the semiconductorwafer to be processed is pressed onto the pad 11 on the polishing table10 by a wafer carrier 14. At the same time, the semiconductor wafer andthe polishing table 10 rotate. The polishing agent 12 is composed insuch a way that it contains both polishing grains and active chemicaladditives. The polishing grains, which generally have a diameter of 20to 50 nm, are used for the mechanical polishing of the surface of thesemiconductor wafer. The chemical additives in the polishing agent 12are matched to the layer material to be removed.

In the chemical-mechanical polishing process illustrated in FIG. 1 forworking out the alignment mark structure, the copper layer 6 is removedin a first polishing process, being stopped on the intermediate layer 5consisting of tantalum/tantalum nitride. The copper polishing process isin this case carried out with a polishing agent based on aluminum oxide.Pan W (Freudenberg) is preferably used as polishing table pad. Thisfirst copper polishing step on the kerf area 1 is preferably carried outat the same time as the copper layer is polished away over thedepressions provided for the conductor tracks.

As FIG. 1B shows, during the copper polishing in the kerf area 1, adishing behavior of the copper areas occurs so that the lands 4 in thedielectric layer 2 stand out from the metal surface 6. However, at thesame time as the dishing of the copper during the polishing process,there is also partial removal of the intermediate layer 5 in the area ofthe lands 4 in the dielectric layer 2, as FIG. 1B further shows.

After the copper polishing step, a second tantalum polishing step iscarried out, in which the intermediate layer 5 on the lands 4 in thedielectric layer 2 is removed. In this case, a polishing agent based oncolloidal silicon oxide is preferably used for the tantalum polishing.Embossed Politex (Rodel) is preferably used as the polishing table pad.In this tantalum polishing step, as FIG. 1C shows, very intensiveremoval of the intermediate layer 5 in the area of the lands 4 takesplace, in which material is also removed from the dielectric layer 2lying underneath. This overpolishing, which leads to erosion of thedielectric layer 2 lying under the intermediate layer, can also beattributed in particular to the fact that a large part of theintermediate layer 5 has already been removed in the copper polishingstep. As a result of the tantalum polishing step, as FIG. 1C shows, theformation of trenches in the area of the lands 4 in the dielectric layer2 occurs between the metal surfaces 6. This trench formation thenensures that a topology of the alignment marks, which is suitable foraligning an exposure device for transferring a mask, then becomesapparent on a layer that is subsequently applied.

The method according to the invention of forming the alignment marks issubstantially based on the model of the damascene technique, but with anintricate structure consisting of a non metal being produced in alarge-area metal layer. This layer structure makes it possible, with theaid of the chemical-mechanical polishing and by using the intrinsicallynegative effects of the dishing of large metal surfaces or the erosionof intricate structures during the polishing operation, to work theintricate structure out of the large metal surface.

In the embodiment presented above, a two-stage polishing process isused, which is suitable in particular for forming alignment marks in acopper metallization plane. The two-stage polishing process presented,in which the copper metal layer 6 is polished away first and then theintermediate layer 5, can, however, also be replaced by a single-stagepolishing process in which only copper polishing is carried out. As aresult of this single polishing process, as shown in FIG. 1B, the lands4 of the dielectric layer 2 then stand out between the metal surfaces,and said layer is then also revealed as a topology on a non transparentlayer deposited thereon. Instead of the use of copper as metal and anintermediate layer of tantalum/tantalum nitride, however, there is alsothe possibility of using another metal or another material for theintermediate layer.

The features of the invention disclosed in the above description, thedrawings and the claims can be important, both individually and in anydesired combination, to implement the invention in its variousconfigurations.

What is claimed is:
 1. A method of applying alignment marks to asemiconductor wafer, the method comprising: producing a non-metalintricate structure in a large-area metal layer in at least one area ofthe semiconductor wafer by forming depressions in a surface area of thesemiconductor wafer, lands being formed between the depressions, andsubsequent deposition of the metal layer over the entire surface area;and planarizing the area of the semiconductor wafer having thelarge-area metal layer by means of chemical-mechanical polishing, sothat the non-metal intricate structure stands out from the large-areametal layer after the polishing process; an additional intermediatelayer being applied between the semiconductor surface and the metallayer; the planarization being carried out in two stages by means ofchemical-mechanical polishing, in the first stage the metal layer beingremoved and being stopped on the intermediate layer lying underneathand, in the second stage, the intermediate layer being removed andstopped in the lands lying underneath; and the first stage beingdesigned in such a way that overpolishing of the metal surfaces betweenthe projecting lands is carried out, the intermediate layer on theprojecting lands also being partly removed at the same time, and thesecond stage being designed in such a way that intensive overpolishingof the intermediate layer is carried out, in which erosion of the landslying underneath takes place, so that trenches result between the metalsurfaces.
 2. The method according to claim 1, in which thechemical-mechanical polishing process is carried out in such a way thatthe large-area metal layer is removed more intensely than the non-metalintricate structure provided therein, so that the intricate structurestands out from the metal layer.
 3. The method according to claim 1, inwhich the chemical-mechanical polishing process is carried out in such away that the non-metal intricate structure is removed more intenselythan the large-area metal layer surrounding it, so that a formation oftrenches of the intricate structure occurs in the metal surface.
 4. Themethod according to claim 1 further comprising forming, on thesemiconductor surface, a dielectric layer, in which the depressions andlands are executed.
 5. The method according to claim 1, wherein themetal layer includes copper.
 6. The method according to claim 1, whereinthe intermediate layer comprises a tantalum/tantalum nitride doublelayer.
 7. The method according to claim 1, further comprising applyingthe alignment marks in a kerf area of the semiconductor wafer.
 8. Amethod of applying an alignment mark to a semiconductor wafer, themethod comprising: providing a semiconductor wafer the wafer havingwalls defining first and second depressions, the first and seconddepressions defining a land therebetween, the intermediate layer beingcoated with a metal layer having a depth sufficient to cover the land;executing a first chemical-mechanical polishing step to remove asufficient depth of the metal layer to expose the land and to partiallyerode a portion of the intermediate layer in contact therewith; andexecuting a second chemical-mechanical polishing step to intensivelyoverpolish the intermediate layer from the exposed land and to erode aportion thereof, thereby forming, on an exposed surface of the land, analignment mark.
 9. The method of claim 8, wherein executing a firstpolishing step comprises eroding the metal layer more rapidly than theland, thereby causing the land to protrude from the metal layer.
 10. Themethod of claim 8, wherein executing a second polishing step compriseseroding the land more rapidly than the metal layer thereby forming atrench in the land.
 11. The method of claim 8, wherein providing asemiconductor wafer comprises providing a wafer coated with a dielectriclayer, the intermediate layer being in contact with the dielectriclayer.
 12. The method of claim 8, wherein providing a semiconductorwafer comprises selecting the metal layer to include copper.
 13. Themethod of claim 8, wherein providing a semiconductor wafer comprisesselecting the intermediate layer to be a tantalum/tantalum nitridedouble layer.
 14. The method of claim 8, wherein providing asemiconductor wafer comprises providing a wafer having a kerf area, themethod further comprising causing the alignment mark to be formed in thekerf area.